1. Field
The described embodiments relate to microprocessors. More specifically, the described embodiments relate to precise data return handling in speculative processors.
2. Related Art
Some modern microprocessors facilitate deferred execution of instructions with unavailable operands. In these processors, if an instruction is ready for execution before all of its operands are available, the processor can place the instruction in a deferred buffer, thereby “deferring” the instruction, and can speculatively execute subsequent non-dependent instructions. While speculatively executing the subsequent instructions, any instruction with unavailable operands is similarly placed in the deferred buffer in program order (including instructions with dependencies on results of instructions which are already in the deferred buffer).
When the operands for a deferred instruction eventually become available, the processor enters a “deferred-execution mode,” during which the processor issues deferred instructions from the deferred buffer in program order for execution. In the deferred-execution mode, any instructions for which all operands are available are executed, but instructions with unavailable operands are placed back into the deferred buffer in program order, thereby “re-deferring” these instructions. In these processors, when each operand becomes available, if there are instructions in the deferred buffer, the processor makes a pass through the deferred buffer in deferred mode to attempt to execute any dependent deferred instructions.
Because the processor makes a pass through the deferred buffer as each operand becomes available, in some cases inefficiencies can arise. For example, assume that:                1. Cache line a, which contains input data for instruction A, is not in the processor's data cache when the processor attempts to execute instruction A, and so the processor defers instruction A and sends a request to the memory system for cache line a.        2. Cache line b, which contains input data for instruction B is not in the processor's data cache when the processor attempts to execute instruction B, and so the processor defers instruction B and sends a request to the memory system for cache line b.        3. Numerous additional instructions that are unrelated to instructions A or B are also deferred because input data is not available for these instructions.When cache line a eventually returns from the memory system, the processor enters the deferred-execution mode and begins to issue the deferred instructions from the deferred buffer for execution. Assuming that cache line b returns after the processor starts execution in the deferred-execution mode, but before the processor executes instruction B, because both cache line a and cache line b are then available, the processor can execute both instructions A and B.        
Because cache line b returned after the processor started in the deferred-execution mode, upon completing the pass through the deferred buffer, the processor automatically starts a second, separate pass through the deferred buffer in the deferred-execution mode to attempt to execute instructions that are dependent on cache line b. However, as described above, the processor was able to execute instruction B in the first pass through the deferred buffer in deferred-execution mode. Thus, the subsequent pass through the deferred buffer triggered by the return of cache line b unnecessarily employs the processor's computational resources, preventing the resources from being used to perform useful computational work.